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Old November 12th, 2004, 08:54 PM     #5 (permalink)
joker_927
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The time the CPU has to detect the "high" or "low" states, is limited by the CPU clock. If the clock is set to higher speed, the time for detection, the "decision cycle", becomes shorter.

The signal itself is not at all digital. Its analogue. Which means, it doesn't jump from "low" to "high" and back in no time, it gradually rises from the lower level to the higher and back. This is caused by parasitic capacitance's and resistors. They are called "parasitic", because you rather would like them not to be there, but given the current semiconductor manufacturing process, you can't avoid them.

In the design of the CPU, it is attempted to keep the parasitics as low as possible. Sometimes you run into a quagmire. If you make the resistance lower (for example wider metal lines have less resistance), you might increase the capacitance (wider metal lines have more capacitance). Which means, you will always end up with having the parasitics in one way or another.



thx!!
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