December 24th, 2001, 12:14 PM
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#1 (permalink)
| | Ultimate Member
Join Date: Oct 2001 Location: Chicago, IL
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How many more Xps will there be? Has there been a month announced for the tbred release? |
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December 24th, 2001, 02:08 PM
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#2 (permalink)
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Join Date: Oct 2001 Location: Willowbrook, IL US
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We'll have to keep on checking those Techie Newspapers on-line to see what AMD might pull off. I'm just hoping that *at least* 3 Palomino XP processors will be released before the Hammer gets released (more likely I'll be seeing a higher revision XP Processor once the Hammer gets released for the public). I'm suspecting that these PRs will be 2000, 2100, and 2200 (1.73, 1.8, and 1.93 I guess respectively).
More likely, the Hammer Processors will probably use a 150MHz and 166MHz Internal Bus Multiplier IMO.
To conclude, just keep on checking those Techie Newspapers on-line to see what AMD might have in store for us. I'm thinking that AMD *might* concentrate more on their HAMMER line of Processors (unsure whether these processors will use a new ZIF PGA Array and/or use the SECC, I pity SECC's) IMO. Maybe the Hammers might provide a higher Internal Bus Multiplier and I'm guessing that these Hammer Processors might support both DDR and Direct Rambus, but I'm thinking that AMD might provide flexibility as far as Memory Type is concerned.
IMO These new Hammers might be using an external FSB of 300-667MHz and might have "Megahertz Myth-fighting" architectures in order to make every "Megahertz" and/or "Gigaflop" count, somewhat similar to that of Apple's G4 Processors.
For now, just keep an eye on new news from the Techie newspapers. AMD *might* release 1-3 more XP Processors depending on how sooner the Hammer Processors gets released. |
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December 24th, 2001, 02:33 PM
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#3 (permalink)
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Join Date: Dec 2001 Location: Wwwwaconia, MMMinnes
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So I'm supposed to keep an eye on the techie newspapers right?
Kidding  |
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December 24th, 2001, 02:38 PM
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#4 (permalink)
| | Registered User
Join Date: Oct 2001
Posts: 664
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well heck. why don't we rename this thread "Tech-Newspaper". LOL! |
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December 24th, 2001, 08:18 PM
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#5 (permalink)
| | Ultimate Member
Join Date: Oct 2001 Location: Israel
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| vesther - not so fast
What about "Thoroughbred" ? It's gonna be quite similar to "Palomino", but manufactured using 0.13um techprocess, maybe with twice bigger L2 cache (like Intel did with "Northwood"). It will come after "Palomino" reaches 2000+ PR-rating. And after "Thoroughbred" there will be "Barton", 0.13um+SOI (silicon-on-insolator, to allow even less power consumption and smaller die).
And only after "Barton" we'll see "Hammer" in mass-production.
Best Regards ... |
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December 24th, 2001, 09:11 PM
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#6 (permalink)
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I was mainly wondering about Thoroughbred and Barton. Any info on those? When do they come out, what speeds, what features, etc? |
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December 24th, 2001, 10:15 PM
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#7 (permalink)
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December 25th, 2001, 05:58 AM
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#8 (permalink)
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Just take a look at AMD's roadmap, thoroughbred and appaloosa are due 1half of 2002. Hammer isn't scheduled until 2nd half I belive it was..... |
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December 25th, 2001, 10:33 AM
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#9 (permalink)
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| Quote: Originally posted by Hellmund Just take a look at AMD's roadmap, thoroughbred and appaloosa are due 1half of 2002. Hammer isn't scheduled until 2nd half I belive it was..... | Exactly, BARTON cores are scheduled to hit the shelves after Thoroughbred. Hammer then comes into play after Barton.
AMD Processor Die Order of Precedence:
* Thoroughbred and Appaloosa (I think this is supposed to be Socket A, might allow an internal FSB of 150-166MHz, not sure if Thoroughbred will have a larger Internal FSB or not, but currently, the largest Internal FSB on an AMD Processor is 133MHz. Palominoes currently have a 266MHz External Front Side Bus. IMO Appaloosas are going to be pretty much Thoroughbred with less On-Die Cache and less power consumption, not sure about this, but IMO Appaloosas might allow full unconditional support for DDR on Duron Systems for the first time. I think that by the time the Appaloosas hit the shelves, IMO Durons could have a 266MHz External FSB, not sure if the Appaloosas will have a new architecture or not.)
* Barton (Might have a larger Internal FSB for both Athlons and Durons, still not sure if this is the case. Athlons are going to have a larger L1 and L2 On-Die Cache and a larger Internal FSB than the Durons as always. I'm guessing that from the Barton, the Athlons will have a 333MHz External Front Side Bus and a 166MHz Internal Front Side Bus for the least. Durons probably going to have larger L1 and L2 On-Die Caches than today's Morgan Cores, but then, I'm not sure if a new die is going to change the architecture of the chip.)
* Hammer (This is what I'm going to be waiting for. I think that Athlons and Durons are going to be using a new PGA ZIF Socket Type for this one IMO. I think that the Hammer will use a more advanced architecture and "Megahertz Myth-fighting" technologies not found on Athlon XP. I'm thinking that the Hammer will have an External Front Side Bus 4 times over the Internal Front Side Bus, but the Internal Front Side Bus and the On-Die Caches could be possibly be larger. I'm not sure if AMD has plans to have any new chips support Direct Rambus RDRAM or not, but I'll keep on checking AMD's progress through various "Techie Resources") |
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December 25th, 2001, 02:45 PM
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#10 (permalink)
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| Quote: Originally posted by Hellmund Just take a look at AMD's roadmap, thoroughbred and appaloosa are due 1half of 2002. Hammer isn't scheduled until 2nd half I belive it was..... | I can't find any updated AMD roadmaps. |
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